1. Field of the Invention
The present invention relates to a method and related apparatus for locking phase, and more particularly, to a method and related apparatus for locking phase with estimated rate modified by rate dithering.
2. Description of the Prior Art
It is one of the most important bases of an information society to transfer and store a great quantity of high-density data in electronic form. This makes interchanges of information and knowledge more convenient. Thus, various circuits for processing, accessing, and transferring electronic signals are now a key to developments in the industry. The phase lock circuit is one of the most important parts of various electronic processing circuits. All the communication systems, digital communication systems and read circuit of a hard disk and a CD-ROM drive use the phase lock circuit to retrieve the clock synchronized with data (i.e. synchronized with baud rate) so that the data can be interpreted correctly.
Please refer to FIG. 1. FIG. 1 is a function block diagram of a phase lock circuit 10 (particularly a digital phase lock circuit) of the prior art. The phase lock circuit 10 comprises an error-test module 14, a filter module 16, a numerical oscillator 18, a detecting circuit 20, a switch circuit 24, and a measuring module 22. Assuming that the phase lock circuit 10 is a digital phase lock circuit, an analog to digital converter 12 can be applied to convert analog signals to digital signals for the convenience of digital data processing. When the phase lock circuit 10 is applied to a communication device or a data storage device (such as a hard disk or a CD-ROM drive) to retrieve the clock synchronized with data, data is often analogically carried in the data signal 30A and inputted to the phase lock circuit 10. For example, the data signal 30A can be a signal received by an antenna and demodulated in a wireless communication system, or a signal read from a magnetic or an optical media (e.g. a hard disk, a magnetic tape or an optical disk) by a pick up head of a hard disk or an optical disk drive. The converter circuit 12 can be triggered by a sampling clock CK0 to sample the data signal 30A in order to form a digital input signal 30B and input it to the phase lock circuit 10. The numerical oscillator 18 can generate a clock 30E, wherein the cycle and frequency of the clock 30E can be changed. A frequency detector 26A and a phase detector 26B can be set in the error-test module 14 to detect the frequency and phase difference between the clock 30E and the input signal 30B, and to transfer the result to the filter module 16. The filter module 16 can turn the testing result from the error-test module 14 into an estimated rate 30C for controlling the oscillation cycle of the numerical oscillator 18. Therefore combining the error-test module 14, the filter module 16, and the numerical oscillator 18 forms a phase lock loop. On the other hand, the input signal 30B is transferred to the measuring module 22 so as to generate an estimated rate 30D according to transitions in the input signal 30B. The estimated rate 30D can also be used to control the oscillation cycle of the clock 30E so as to provide an initial value for the phase lock process of the phase lock circuit. To generate an initial value by using the digital input signal 30B, a zero-crossing detector 28A, a sampling counter 28B, and a counter circuit 28C can be set in the measuring module 22. The detecting circuit 20 of the phase lock circuit 10 is for controlling the switch circuit 24 according to the result from the error-test module 14. This allows controlling the numerical oscillator 18 according to either the estimated rate 30C from the filter module 16 or the estimated rate 30D from the measuring module 22.
Please refer to FIG. 2. FIG. 2 is a timing diagram of related waveforms and phase lock process of the phase lock circuit 10 in the prior art, where the horizontal axis represents time. Waveform timing diagrams of a data clock CKd, a data signal 30A, and an input signal 30B are shown from top to bottom in the upper part of FIG. 2, where the vertical axis represents amplitude. The curve 32 shows in FIG. 2 represents the transitions in estimated rate 30D, wherein the vertical axis represents the magnitude of the estimated rate. The curve 34 shown in FIG. 2 represents the frequency transitions in clock 30E (i.e. frequency transitions of the numerical oscillator 18), wherein the vertical axis represents the magnitude of frequency. As the data signal 30A shows in FIG. 2, pluralities of data are carried in data signal 30A, and each data corresponds to a cycle Td of the data clock CKd. In other words, the frequency of data clock CKd corresponds to the baud rate of data signal 30A. For example, three successive high-levels of data cycle Td at T0 represent three successive digital data [1], and two successive low-levels of data cycle Td at T1 represent two successive digital data [0]. This shows the data signal 30A must be interpreted correctly only by referring to the data clock CKd. For example, the numbers of digital data [1] at T1 cannot be recognized without referring to the data clock CKd.
In the application of modern electronic circuits, however, the data clock CKd is not generally transferred with the data signal 30A. In other words, the data signal 30A is interpreted without referring to the data clock CKd. In this case, the phase lock circuit 10 retrieves the clock synchronized with the data in the data signal 30A to interpret the data signal 30A. The clock 30E generated by the numerical oscillator 18 can be regarded as a data clock of the data signal 30A after the phase lock is stable. If a digital phase lock circuit 10 retrieves the data clock corresponding to data signal 30A, the data signal 30A is transferred to a digital input signal 30B by an analog to digital converter 12 in coordination with a sampling clock CK0. As shown in FIG. 2, the interval of each sampling point in input signal 30B is the sampling cycle Ts of the sampling clock CK0. The input signal 30B is then sent to both the phase lock loop and the measuring module 22.
In favor of retrieving the data clock, all data in data signal 30A are encoded so that each data in data signal 30A has a particular statistical characteristic after combination. For example, the data recorded on an optical disk are encoded, after being decoded to the data signal 30A every 1024 data (i.e. 1024 data clock cycle) have 216 data transitions on average. The data transition means the digital data is transferred from [1] to [0], or from [0] to [1]. Correspondingly, a zero-level between the high-level and low-level of the input signal 30B, sampled from the data signal 30A, can be defined (as L0 shown in FIG. 2). The data transition represents a data zero-crossing (i.e. crossing the zero-level) in the input signal 30B. For example, three zero-crossings corresponding to three data transitions occur at t3, t4, and t5. The input signal 30B crosses the zero-level from low-level to high-level at t3, and crosses the zero-level from high-level to low-level at t4. The measuring module 22 can count the zero-crossing numbers in input signal 30B by using this particular statistical characteristic. Statistically, there are 216 zero-crossings in every 1024 data. The total required time of 216 zero-crossings calculated by the measuring module 22 can be regarded as the cycle of 1024 data clocks. According to this theory, the measuring module 22 can measure the frequency of data clock and generate a corresponding estimated rate 30D.
The frequency estimation is achieved in the following steps. Counting the accumulative zero-crossing numbers by the zero-crossing detector 28A, calculating the numbers of sampling cycles Ts during the zero-crossing accumulation period by the sampling counter 28B triggered by the sampling clock CK0, and eventually calculating the estimated rate for controlling the numerical oscillator 18. In the preceding example, if there are 216 zero-crossings in every 1024 data of the data signal 30A and the input signal 30B, when the zero-crossing detector 28A begins to count the accumulative zero-crossing numbers in the input signal 30B, the sampling counter 28B will be triggered simultaneously to count the sampling point numbers. Since the sampling cycle Ts is fixed, the total required time can be known by counting the sampling point numbers (i.e. counting the numbers of sampling cycles). When the zero-crossing numbers accumulate to 216, the sampling counter will stop counting the sampling point numbers. Using a shift register of the calculating circuit 28C to divide the sampling point numbers by 1024 can obtain the average numbers of sampling cycles (also called OSR, Over Sampling Rate). Since the sampling cycle Ts is fixed, the result of above calculation represents how long the data lasts, which means how long the cycle Td of the data clock is. Similarly, the estimated rate 30B is obtained. In practice, the measuring module 22 starts to count the accumulative zero-crossing numbers at intervals to obtain a series of estimated rates. For example, as the curve 32 shows in FIG. 2, which represents the estimated rate 30D. The measuring module 22 starts to count the accumulative numbers of the zero-crossings at t0, t1, and t2. If the accumulative counting of zero-crossings starts at t0 and accumulates to 216 at t3, the measuring module 22 will generate an estimated rate 30D (r3 shown in FIG. 2) according to the accumulative numbers of input signal sampling points from t0 to t3 (effectively, the duration from t0 to t3). Similarly, if the accumulative calculation of zero-crossings starts at t1 and accumulates to 216 at t4, the measuring module 22 will generate another estimated rate 30D (r4). For this reason the measuring module 22 can generate a series of estimated rates 30D (r3 to r5) at t3, t4, t5, etc.
The characteristic “216 zero-crossing in every 1024 data”, however, is a macro statistical characteristic. Theoretically, the preceding characteristic requires an infinite series of input signals 30B to carry out. If a finite data series is used, the result could be a random value near 1024 (e.g. 1022 and 1023 or 1025 and 1026). Also, the estimated rate 30D generated by the measuring module 22 will be a random distribution as the curve 32 shows in FIG. 2. Since the duration used to calculate different estimated rates overlaps, the estimated rates are correlative. For example, the estimated rate at t3 is calculated according to the input signal 30B from t0 to t3, and the estimated rate at t4 is calculated according to the input signal 30B from t1 to t4. Thus the estimated rates at t3 and t4 are both relevant to the input signal 30B from t1 to t3. That is to say the estimated rates at t3 and t4 are not statistically independent.
The measuring module 22, the error-test module 14 and the filter module 16 that are connected to the numerical oscillator 18 through a switch circuit 24 can form a typical feedback phase lock loop. After the input signal 30B and the clock 30E being compared by the error-test module 14, the comparison result is fed back to the numerical oscillator 18 to adjust the frequency (or phase) of the clock 30E through the filter module 16 connected to the switch circuit 24. During the repeating process of error testing and frequency adjusting, the clock 30E and the input signal 30B will be eventually synchronized so that the clock 30E can be locked as the data clock of the input signal 30B. However, the above-mentioned phase lock loop is not valid unless the frequency of the clock 30E and the proper baud rate of the input signal 30B (data signal 30A) are nearly. Therefore, a detecting circuit is installed in the phase lock circuit 10 to control the switch circuit 24 so that the numerical oscillator 18 can select the estimated rate 30D from the measuring module 22 or the estimated rate 30C from the filter module 16 to adjust the frequency of the clock 30E. As the curve 34 shows in FIG. 2, the frequency fc represents the frequency of the clock corresponding to the input signal 30B. The function of the phase lock circuit 10 is to lock the clock 30E frequency to fc. The frequency fb0 and fb1 represent the range where the phase lock circuit is available. In other words, if the frequency of the clock 30E is located between fb0 and fb1, the phase lock circuit can lock the clock 30E frequency to fc effectively. On the other hand, the phase lock circuit is not valid if the frequency of the clock 30E is out of the range. In this case, the estimated rate 30D from the measuring module 22 is used to readjust the frequency of the clock 30E.
In summary, the phase lock process of the phase lock circuit 10 is described as follows. When the measuring module 22 is still counting the accumulative zero-crossing numbers and not capable of providing a new estimated rate 30D, the detecting circuit 20 will control the switch circuit 24 to make the numerical oscillator 18 electrically connect to the filter module 16, then the phase lock loop will be conducted to feed the estimated rate 30C from the filter module 16 back to the numerical oscillator 18 to control the frequency of the clock 30E. When the accumulative zero-crossing numbers accumulates to a predetermined value (such as 216), the measuring module 22 will generate a new estimated rate 30D, and the detecting circuit 20 will determine the synchronization between the clock 30E and the input signal 30B according to the comparative result from the error-test module 14. If the phase (and/or the frequency) error is larger than a predetermined value, the frequency of the clock 30E is probably out of the range between fb0 and fb1. In this case, the phase lock loop is not valid. The detecting circuit 20 will then switch the switch circuit 24 to allow the numerical oscillator 18 to use the estimated rate 30D from the measuring module 22 and readjust the frequency of the clock 30E. After that, the detecting circuit 20 will switch the switch circuit 24 to continue the phase lock process. Relatively, if the comparative result from the error-test module 14 is smaller than a predetermined value, which means the frequency of the clock 30E is located in the range between fb0 and fb1, the phase lock loop will continue to synchronize the clock 30E and the input signal 30B. In this case the detecting circuit 20 will not switch the switch circuit 24. For example, as the curve 34 shows in FIG. 2, before t3 the frequency of the clock 30E is controlled by the phase lock loop, and at t3 the measuring module 22 will generate a new estimated rate 30D (i.e. r3). Simultaneously the detecting circuit 20 determines that the frequency of the clock 30E is out of the range of fb0 and fb1, the detecting circuit 20 will then switch the switch circuit 24 so as to allow the numerical oscillator 18 to use the estimated rate 30D and adjust the frequency of the clock 30E to f3 (corresponding to r3). After that the switch circuit 24 will be switched again so as to allow the phase lock circuit to adjust the frequency of the clock 30E. When the phase lock loop continuously operates from t3 to t4, the measuring module 22 will generate a new estimated rate 30D (i.e. r4) according to the accumulative zero-crossing numbers. The detecting module 20 will detect the synchronization error of the clock 30E and the input signal 30B again. If the error is too large, the detecting circuit 20 will switch the switch circuit 24 so as to allow the numerical oscillator 18 to adjust the frequency of the clock 30E to f4 (corresponding to r4) according to the estimated rate 30D at t4. After that, the switch circuit 24 will be controlled by the phase lock loop again. The phase lock loop will continuously operates from t4 to t5. After that, because the synchronization error is too large, the switch circuit 24 will be switched so that the frequency of the clock 30E will be adjusted to f5 (corresponding to r5) according to the estimated rate 30D at t5 (i.e. r5). Because f5 is located between fb0 and fb1, the frequency of the clock 30E and the input signal 30B can be synchronized in the phase lock process. The detecting circuit 20 will not switch the switch circuit 24 even when the measuring module 22 generates a new estimated rate because the synchronization error is smaller than a predetermined value, and the phase lock loop will continue operating to synchronize the frequency of the clock 30E and the input signal 30B.
The estimated rate 30D generated by the measuring module 22 is an initial value for the phase lock loop. If the frequency corresponding to the estimated rate 30D is between fb0 and fb1, the frequency of the clock 30E will be locked and synchronized in the following phase lock process. On the other hand, if the frequency corresponding to the estimated rate 30D is out of the range between fb0 and fb1, the frequency of the clock 30E cannot be synchronized in the following phase lock process. Therefore, the key to the phase lock circuit 10 is whether the estimated rate 30D falls between fb0 and fb1. As discussed above, however, the estimated rate 30D generated by the measuring module 22 in the prior art at different times are statistically correlative. In other words, if the statistical characteristic of the input signal 30B in a period of time deviates, then all of the estimated rate 30D derived from the same period of time will deviate the frequency corresponding to the proper baud rate so that successive estimated rates may not be between fb0 and fb1. Following the above-mentioned example, according to the macro statistical character of the input signal 30D, there are 216 zero-crossings in every 1024 data. But if there are 216 zero-crossings in every 1000 data during a certain period of time, all the estimated rates estimated by the measuring module 22 during this period of time will be higher than the frequency corresponding to the proper baud rate. In this case, even the detecting circuit 20 uses these estimated rates to adjust the frequency of the clock 30E, and the phase lock process cannot be accomplished in a short time. This is the reason why the phase lock process requires more time in the prior art.